Monolithic MOSFET and schottky diode for mobile phone boost converter

ABSTRACT

A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power metal oxide semiconductor field effect transistor (MOSFET) and Schottky diode. The semiconductor device has the lateral diffused MOSFET formed on a surface of the semiconductor device. The MOSFET is formed with a plurality conduction fingers. The Schottky diode is also formed on the surface of the semiconductor device and integrated between the plurality of conduction fingers of the MOSFET. The drain of the MOSFET is connected to the anode of the diode on the surface of the monolithic semiconductor device.

CLAIM TO DOMESTIC PRIORITY

The present non-provisional patent application claims priority toprovisional application Ser. No. 60/646,120, entitled “Monolithic MOSFETand Schottky Diode for Mobile Phone Boost Converter,” and filed on Jan.21, 2005, by Anderson et al.

FIELD OF THE INVENTION

The present invention relates in general to electronic circuits andsemiconductor devices and, more particularly, to an integrated ormonolithic MOSFET and Schottky diode for mobile phone boost converters.

BACKGROUND OF THE INVENTION

Most modern electronic equipment require a power supply to provide adirect current (DC) operating potential to the electronic componentscontained therein. Common types of electronic equipment which use DCpower supplies include cell phones, personal computers, energy systems,telecommunication systems, audio-video equipment, consumer electronics,automotive components, and other devices which utilize integratedcircuits, semiconductor chips, or otherwise require DC operatingpotential. Most, if not all, semiconductor components require a lowvoltage DC operating potential.

Not all semiconductor devices or electronic components operate with thesame DC potential. Some integrated circuits (ICs) or discretesemiconductor devices require a higher DC supply voltage than others. Acommon approach in electronic systems requiring multiple DC operatingvoltage levels is to convert a base DC operating potential to othervoltage levels. For example, the battery or main power supply to theelectronic system may provide 3 volts DC. One or more DC/DC boostconverters within the electronic system increase the voltage level tosay 5 volts DC or 12 volts DC to supply power to certain componentswithin the system.

The DC/DC boost converter uses an inductor or coil having a firstterminal coupled to the converter input and power metal oxidesemiconductor field effect transistor (MOSFET) coupled between a secondterminal of the coil and ground. The conduction through MOSFET iscontrolled by a pulse width modulated (PWM) controller. The PWMcontroller turns on the power MOSFET to enable a current conduction paththrough the coil and thereby store energy in the coil. When the PWMcontroller turns off the power MOSFET, the energy stored in the coil istransferred through a Schottky diode to an output of the DC/DC boostconverter. The output voltage of the converter is used to generate afeedback signal to the PWM controller to control the on-time of thepower MOSFET and regulate the DC output voltage of the boost converter.

The power MOSFET and Schottky diode are typically discrete components inthe DC/DC boost converter. In some electronic systems, such as cellularphones, space on the printed circuit board (PCB) is a premium. As cellphones reduce in feature size, the space required for discretecomponents becomes a design issue. In addition to surface arealimitations, the need for low profile and small footprint semiconductordevices continues to grow as cell phones become thinner and smaller indesign.

A need exists for semiconductor devices and packages that are compatiblewith electronic systems having limited surface areas and low profiles.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is a monolithic semiconductordevice, comprising a lateral double diffused metal oxide semiconductorfield effect transistor (LDMOSFET) formed with a plurality conductionfingers on a surface of the monolithic semiconductor device. A diode isformed on the surface of the monolithic semiconductor device andintegrated between the plurality of conduction fingers of the LDMOSFET.A first conduction terminal of the LDMOSFET is connected to a firstterminal of the diode on the surface of the monolithic semiconductordevice.

In another embodiment, the present invention is a semiconductor package,comprising a monolithic semiconductor device including a lateral doublediffused metal oxide semiconductor field effect transistor formed on asurface of the monolithic semiconductor device and a diode formed on thesurface of the monolithic semiconductor device and integrated between aplurality of conduction fingers of the LDMOSFET.

In another embodiment, the present invention is a monolithicsemiconductor device, comprising a lateral double diffused metal oxidesemiconductor field effect transistor formed with a plurality conductionfingers on a surface of the monolithic semiconductor device. A diode isformed on the surface of the monolithic semiconductor device andintegrated between the plurality of conduction fingers of the LDMOSFET.

In another embodiment, the present invention is a method of making amonolithic semiconductor device comprising the steps of forming alateral double diffused metal oxide semiconductor field effecttransistor with a plurality conduction fingers on a surface of themonolithic semiconductor device, and forming a diode on the surface ofthe monolithic semiconductor device integrated between the plurality ofconduction fingers of the LDMOSFET.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cellular telephone with a printed circuit boardcontaining integrated circuits and semiconductor devices;

FIG. 2 is a schematic diagram of a DC/DC boost converter;

FIG. 3 is a monolithic integrated circuit package containing the powerMOSFET and Schottky diode of FIG. 2;

FIG. 4 is a cross-sectional view of the monolithic power MOSFET andSchottky diode; and

FIG. 5 is a top view of the monolithic power MOSFET and Schottky diode.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the Figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving the invention'sobjectives, it will be appreciated by those skilled in the art that itis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and their equivalents as supported by the followingdisclosure and drawings.

Referring to FIG. 1, a cellular phone 10 is shown having a front body 12housing keyboard 14 and liquid crystal display (LCD) 16. Cell phone 10further includes a rear body 20 housing PCB 22. PCB 22 is separated intoradio frequency (RF) signal processing section 24 and digital signalprocessing section 26, separated by shielding. The RF signal processingsection 24 includes electronic components such as RF amplifier,modulator, demodulator, oscillator, and power management. The RF signalprocessing section receives RF signals, downconverts, and demodulatesthe signals to baseband signals. The digital signal processing section24 includes electronic components such as microprocessor, analog todigital converter, digital to analog converter, memory, and controllogic. The digital signal processing section 26 processes the basebandinformation so the user can hear and speak over the cell phone.

Many of the electronic components on PCB 22 may require different DCoperating potentials. Cell phone 10 has one lithium-ion battery source,e.g. 3.6 volts DC, attached to rear body 20. To convert the 3.6 VDCbattery voltage to other operating potentials, one or more DC/DC boostconverters are designed into PCB 22. The DC/DC boost converter generatesDC operating potentials, e.g. 5 VDC or higher, for the electroniccomponents which require a power supply different than the 3.6 VDCbattery voltage.

The space limitations of PCB 22 in cell phone 10 dictate that the use ofdiscrete components should be minimized and eliminated where possible.The semiconductor die or device within each discrete component is smallcompared to its overall package size. The same issue exists with otherelectronic systems having space limitations, such as radios, two-waypagers, digital recorders, laptop computers, compact disk players,compact video players, and the like. To support this design preference,in the following description, the power MOSFET and Schottky diode of theDC/DC boost converter are integrated into a single monolithic package.

In addition, other electronic systems that do not necessarily have spacelimitations, e.g. personal computers, energy systems, telecommunicationsystems, audio-video equipment, consumer electronics, and automotivecomponents, can benefit from the cost savings and design efficienciesassociated with the integration of discrete components.

A DC/DC boost converter 40 is shown in FIG. 2. A DC input voltage V_(IN)from the battery source is applied to input terminals 42 and 44. Aninductor or coil 46 is coupled between terminal 42 and Schottky diode48. An n-channel power MOSFET 50 has a drain terminal coupled to theanode of diode 48 and a source terminal coupled to terminal 44. MOSFET50 is a 25V lateral diffused power MOSFET with a drain source resistance(R_(DSon)) of 0.25 ohms with gate voltage of 2.5 V. The total gatecharge of MOSFET 50 is 0.5 nC (5V). Parasitic diode 52 is shown acrossthe conduction terminals of power MOSFET 50. Diode 48 is a 25V Schottkydiode with forward voltage drop less than 0.35V. The cathode of diode 48is coupled to output terminal 54. Capacitor 58 is coupled across theoutput terminals of the converter for filtering and energy storage.DC/DC boost converter 40 provides DC output voltage V_(OUT) having avoltage level different from V_(IN). The DC output voltage V_(OUT) isused to provide operating potential to one or more of the electroniccomponents in RF signal processing section 24 and/or digital signalprocessing section 26.

The output voltage VOUT is used to generate a feedback (FB) signal,which is applied to PWM controller 56. PWM controller 56 generates a PWMcontrol signal which is applied to the gate of power MOSFET 50. PWMcontroller 56 controls the conduction time of MOSFET 50 during eachcontrol cycle. If the output voltage V_(OUT) falls, due to an increasingload, the duty cycle of the PWM control signal increases to lengthen theon-time of MOSFET 50 within the control cycle. Diode 48 is reversedbiased to isolate the converter output during the on-state of theMOSFET. The longer conduction period of MOSFET 50 stores more energy incoil 46. During the off-time of the MOSFET, diode 48 becomes forwardbiased and the energy stored in coil 46 is transferred to the converteroutput to charge capacitor 58 and increases the output voltage V_(OUT).If the output voltage V_(OUT) rises, due to a decreasing load, the dutycycle of the PWM control signal decreases to shorten the on-time ofMOSFET 50 during the control cycle. Again, diode 48 is reversed biasedto isolate the converter output during the on-state of the MOSFET. Theshorter conduction period of MOSFET 50 stores less energy in coil 46.During the off-time of the MOSFET, diode 48 becomes forward biased andthe lesser amount of energy stored in coil 46 is transferred to theconverter output to charge capacitor 58 so as to decrease the outputvoltage V_(OUT).

In the present embodiment, power MOSFET 50 and Schottky diode 48 areintegrated into a single, chip-scale, monolithic package 60 having a1.15×1.15 square millimeter (mm²) footprint. The height of package 60 is0.8 mm to accommodate the low profile requirement. The power MOSFEToccupies about 23% of the die area (0.28 mm²), while the Schottky diodeoccupies about 60% of the die area (0.72 mm²).

As shown in FIG. 3, package 60 is a four-terminal flip-chip combo devicecontaining power MOSFET 50 and Schottky diode 48. Bumps 62-68 are formedon the flip-chip package. Bump 62 is the source of power MOSFET 50 andis electrically coupled to ground terminal 44; bump 64 is the gate ofpower MOSFET 50 and is electrically coupled to the output of PWMcontroller 56; bump 66 is the common drain of power MOSFET 50 and anodeof diode 48 and is electrically coupled to the second terminal of coil46; bump 68 is the cathode of diode 48 and is electrically coupled tooutput terminal 54. Alternatively, in an IC package with external pins,e.g. SOP or DIP, the external connections from the semiconductor die tothe package can be made by wire bonds.

Package 60 occupies significantly less space than conventional discretecomponents providing the same function. In fact, package 60 uses 68%less space on PCB 22 as compared to a conventional discrete MOSFETalone. The difference is more pronounced when taking into account adiscrete Schottky diode and interconnecting PCB tracks. The smallfootprint and low profile of package 60 is applicable to systemsrequiring efficient and compact components, such as DC/DC boostconverters used in cellular phones.

Further detail of the monolithic semiconductor device 78 including powerMOSFET 50 and Schottky diode 48 is shown in FIG. 4. The semiconductordevice 78 uses a lateral double diffused MOSFET structure. The lateraldouble diffused power MOSFET 50 and Schottky diode 48 are formed on thesurface of semiconductor device 78.

In the cross-sectional view, substrate 80 is made of p-typesemiconductor material and provides structural support. The followingregions and layers are formed on substrate 80 using semiconductormanufacturing processes understood by those skilled in the art. Themanufacturing processes includes layering, patterning, doping, and heattreatment. In the layering process, materials are grown or deposited onthe substrate by techniques involving thermal oxidation, nitridation,chemical vapor deposition, evaporation, and sputtering. Patterninginvolves use of photolithography to mask areas of the surface and etchaway undesired material. The doping process injects concentrations ofdopant material by thermal diffusion or ion implantation.

Using the above semiconductor manufacturing processes, a P-well region82 is formed on substrate 80. A body region 84 made with P-material isformed over or above P-well region 82. P+ body 86 and N+ source region88 are formed over or above P− body region 84. Terminal 89 is connectedto N+ source region 88 to provide the source terminal of power MOSFET50. Terminal 89 electrically connects to bump 62. An N-drift region 90and N+ drain region 92 are formed above P-well region 82. Oxide layer 96is formed over N+ source region 88, P− body region 84, and N-driftregion 90. Gate region 98 is formed over oxide layer 96. Terminal 99 iscoupled to gate region 98 to provide the gate terminal of power MOSFET50. Terminal 99 electrically connects to bump 64.

Using the above semiconductor manufacturing processes, an N-drift region100 and N+ region 102 are formed over or above P-well region 82. A metallayer 104 is formed over or above N-drift region 100 and furtherconnects to N+ drain region 92 to provide terminal 105. Metal layer 104may be made with titanium (Ti) or titanium nitride (TiN). The metallayer junction with the lightly doped N-drift region 100 forms theSchottky diode. The metal layer 104 contact to the heavier doped N+drain region 92 forms an ohmic contact. Terminal 105 is the commonterminal for the drain of power MOSFET 50 and the anode of diode 48.Terminal 106 is connected to N+ region 102 which forms the cathode ofdiode 48. Terminals 105 and 106 electrically connect to bumps 66 and 68,respectively.

FIG. 5 illustrates a top view of a portion of semiconductor device 78.MOSFET 50 is formed with a repeating pattern of source and drainconduction fingers, i.e. source, drain, drain, source, source, drain,drain, source, etc. The N-drift regions 100 and N+ regions 102 of diode48 are integrated between the repeating pattern of MOSFET conductionfingers for efficiency of space and design layout. In FIG. 5, therepeating pattern is shown as P+ body 86, N+ region 88 (source), gateregion 98, N-drift region 90, N+ region 92 (drain), P-well region 82(isolation), N-drift region 100 (anode), N+ region 102 (cathode),N-drift region 100 (anode), P-well region 82 (isolation), N+ region 92(drain), N-drift region 90, gate region 98, N+ region 88 (source), andP+ body 86. The lateral diffused MOS structure provides access to thedrain on the surface of the semiconductor device 78. The drain of powerMOSFET 50 on the surface can be readily connected to the anode of diode48 by terminal jumper 105.

In another application, diode 48 may be formed in semiconductorstructure 78 as a Zener diode. The Zener diode would be formed in thesurface of semiconductor structure 78 and be commonly connected toMOSFET 50 as described above.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

1. A monolithic semiconductor device, comprising: a lateral doublediffused metal oxide semiconductor field effect transistor (LDMOSFET)formed with a plurality conduction fingers on a surface of themonolithic semiconductor device; and a diode formed on the surface ofthe monolithic semiconductor device and integrated between the pluralityof conduction fingers of the LDMOSFET, wherein a first conductionterminal of the LDMOSFET is connected to a first terminal of the diodeon the surface of the monolithic semiconductor device.
 2. The monolithicsemiconductor device of claim 1, further including a semiconductorpackage enclosing the LDMOSFET and diode and having four externalconnections.
 3. The monolithic semiconductor device of claim 2, whereinthe semiconductor package has a first connection coupled to a firstconduction terminal of the LDMOSFET.
 4. The monolithic semiconductordevice of claim 3, wherein the semiconductor package has a secondconnection commonly coupled to a second conduction terminal of theLDMOSFET and a first terminal of the diode.
 5. The monolithicsemiconductor device of claim 4, wherein the semiconductor package has athird connection coupled to a second terminal of the diode.
 6. Themonolithic semiconductor device of claim 5, wherein the semiconductorpackage has a fourth connection coupled to a control terminal of theLDMOSFET.
 7. The monolithic semiconductor device of claim 1, wherein theplurality of conduction fingers of the LDMOSFET include a repeatingpattern of source and drain conduction fingers.
 8. The monolithicsemiconductor device of claim 7, wherein drift regions of the diode areintegrated between the repeating pattern of source and drain conductionfingers of the LDMOSFET.
 9. A semiconductor package, comprising amonolithic semiconductor device including a lateral double diffusedmetal oxide semiconductor field effect transistor (LDMOSFET) formed on asurface of the monolithic semiconductor device and a diode formed on thesurface of the monolithic semiconductor device and integrated between aplurality of conduction fingers of the LDMOSFET.
 10. The semiconductorpackage of claim 9, wherein a first connection of the semiconductorpackage is coupled to a first conduction terminal of the LDMOSFET. 11.The semiconductor package of claim 10, wherein a second connection ofthe semiconductor package is commonly coupled to a second conductionterminal of the LDMOSFET and a first terminal of the diode.
 12. Thesemiconductor package of claim 11, wherein a third connection of thesemiconductor package is coupled to a second terminal of the diode. 13.The semiconductor package of claim 12, wherein a fourth connection ofthe semiconductor package is coupled to a control terminal of theLDMOSFET.
 14. The semiconductor package of claim 9, wherein theplurality of conduction fingers of the LDMOSFET include a repeatingpattern of source and drain conduction fingers.
 15. The semiconductorpackage of claim 14, wherein drift regions of the diode are integratedbetween the repeating pattern of source and drain conduction fingers ofthe LDMOSFET.
 16. A monolithic semiconductor device, comprising: alateral double diffused metal oxide semiconductor field effecttransistor (LDMOSFET) formed with a plurality conduction fingers on asurface of the monolithic semiconductor device; and a diode formed onthe surface of the monolithic semiconductor device and integratedbetween the plurality of conduction fingers of the LDMOSFET.
 17. Themonolithic semiconductor device of claim 16, further including asemiconductor package enclosing the LDMOSFET and diode and having fourexternal connections.
 18. The monolithic semiconductor device of claim17, wherein the semiconductor package has a first connection coupled toa first conduction terminal of the LDMOSFET.
 19. The monolithicsemiconductor device of claim 18, wherein the semiconductor package hasa second connection commonly coupled to a second conduction terminal ofthe LDMOSFET and a first terminal of the diode.
 20. The monolithicsemiconductor device of claim 19, wherein the semiconductor package hasa third connection coupled to a second terminal of the diode.
 21. Themonolithic semiconductor device of claim 20, wherein the semiconductorpackage has a fourth connection coupled to a control terminal of theLDMOSFET.
 22. The monolithic semiconductor device of claim 16, whereinthe plurality of conduction fingers of the LDMOSFET include a repeatingpattern of source and drain conduction fingers.
 23. The monolithicsemiconductor device of claim 22, wherein drift regions of the diode areintegrated between the repeating pattern of source and drain conductionfingers of the LDMOSFET.
 24. A method of making a monolithicsemiconductor device, comprising: forming a lateral double diffusedmetal oxide semiconductor field effect transistor (LDMOSFET) with aplurality conduction fingers on a surface of the monolithicsemiconductor device; and forming a diode on the surface of themonolithic semiconductor device integrated between the plurality ofconduction fingers of the LDMOSFET.
 25. The method of claim 24, furtherincluding forming the plurality of conduction fingers of the LDMOSFET asa repeating pattern of source and drain conduction fingers.
 26. Themethod of claim 25, further including integrating drift regions of thediode between the repeating pattern of source and drain conductionfingers of the LDMOSFET.